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| PRELIMINARY KM681002B, KM681002BI Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Preliminary PRELIMINARY CMOS SRAM Revision History Rev No. Rev. 0.0 Rev.1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary 2.2. Delete 32-SOJ-300 package 2.3. Delete L-version. 2.4. Delete Data Retention Characteristics and Waveform. 2.5. Add Capacitive load of the test environment in A.C test load 2.6. Change D.C characteristics Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) Icc 160/150/140mA 160/155/150mA Isb 30mA 50mA Draft Data Apr. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary Rev.2.0 Feb. 25th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers. -1- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI 128K x 8 Bit High-Speed CMOS Static RAM FEATURES * Fast Access Time 8,10,12ns(Max.) * Low Power Dissipation Standby (TTL) : 50 mA(Max.) (CMOS) : 10 mA(Max.) Operating KM681002B - 8 : 160 mA(Max.) KM681002B - 10 : 155 mA(Max.) KM681002B - 12 : 150 mA(Max.) * Single 5.0V 10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Standard Pin Configuration KM681002BJ : 32-SOJ-400 KM681002BT: 32-TSOP2-400F Preliminary PRELIMINARY CMOS SRAM GENERAL DESCRIPTION The KM681002B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward. ORDERING INFORMATION KM681002B -8/10/12 KM681002BI -8/10/12 Commercial Temp. Industrial Temp. PIN CONFIGURATION (Top View) A0 1 2 3 4 5 6 7 8 9 32 A16 31 A15 30 A14 29 A13 28 OE 27 I/O8 26 I/O7 FUNCTIONAL BLOCK DIAGRAM A1 A2 A3 Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 Pre-Charge Circuit CS I/O1 I/O2 Vcc SOJ/ TSOP2 25 Vss 24 Vcc 23 I/O6 22 I/O5 21 A12 20 A11 19 A10 18 17 A9 A8 Row Select Vss Memory Array 256 Rows 512x8 Columns I/O3 10 I/O4 11 WE A4 A5 12 13 14 15 16 I/O1~I/O8 Data Cont. CLK Gen. I/O Circuit Column Select A6 A7 PIN FUNCTION A8 A9 A10 A11 A12 A13 A14 A15 A16 Pin Name A0 - A16 Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection CS WE OE WE CS OE I/O1 ~ I/O8 VCC VSS N.C -2- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V SS Voltage on VCC Supply Relative to V SS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V Preliminary PRELIMINARY CMOS SRAM W C C C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0 to 70C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC + 0.5** 0.8 Unit V V V V NOTE: The above parameters are also guaranteed at industrial temperature range. * VIL(Min) = -2.0V a.c(Pulse Width6ns) for I20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width6ns) for I20mA DC AND OPERATING CHARACTERISTICS (TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 8ns 10ns 12ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1* Min -2 -2 2.4 Max 2 2 160 155 150 50 10 0.4 3.95 mA mA V V V Unit A A mA NOTE: The above parameters are also guaranteed at industrial temperature range. * VCC=5.0V, Temp.=25C CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 6 Unit pF pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI AC CHARACTERISTICS (TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads NOTE: The above test conditions are also applied at industrial temperature range. Value 0V to 3V 3ns 1.5V See below Preliminary PRELIMINARY CMOS SRAM Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 +5.0V DOUT VL = 1.5V ZO = 50 30pF* DOUT 255 480 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD KM681002B-8 Min 8 3 0 0 0 3 0 Max 8 8 4 4 4 8 KM681002B-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 5 10 KM681002B-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 Unit ns ns ns ns ns ns ns ns ns ns ns NOTE: The above parameters are also guaranteed at industrial temperature range. -4- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width( OE High) Write Pulse Width( OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW KM681002B-8 Min 8 6 0 6 6 8 0 0 4 0 3 Max 4 KM681002B-10 Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 KM681002B-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 Unit ns ns ns ns ns ns ns ns ns ns ns Preliminary PRELIMINARY CMOS SRAM NOTE: The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Valid Data tAA Valid Data (Address Controlled, CS=OE=VIL, WE=VIH) tRC TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) Valid Data tPU 50% tPD 50% tOH tHZ(3,4,5) CS tOHZ -5- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. Preliminary PRELIMINARY CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5) TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tWR(5) tWP1(2) tDH -6- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) Preliminary PRELIMINARY CMOS SRAM tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5) High-Z tLZ tWHZ(6) Data Valid High-Z Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS H L L L WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC * NOTE : X means Dont Care. -7- Rev 2.0 February 1998 PRELIMINARY KM681002B, KM681002BI PACKAGE DIMENSIONS 32-SOJ-400 #32 #17 Preliminary PRELIMINARY CMOS SRAM Units:millimeters/Inches 10.16 0.400 11.18 0.12 0.440 0.005 9.40 0.25 0.370 0.010 0.20 #1 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 +0.10 -0.05 +0.004 0.017 -0.002 #16 0.69 0.027 MIN 0.008 +0.10 -0.05 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 ( 0.95 ) 0.0375 0.43 1.27 0.050 0.71 +0.10 -0.05 0.028 +0.004 -0.002 32-TSOP2-400F 0~8 0.25 ( 0.010 ) #32 #17 0.45 ~0.75 0.018 ~ 0.030 11.76 0.20 0.463 0.008 10.16 0.400 #1 21.35 MAX 0.841 20.95 0.10 0.825 0.004 #16 0.15 +0.10 -0.05 0.006 +0.004 -0.002 ( 0.50 ) 0.020 1.00 0.10 0.039 0.004 ( 0.95 ) 0.037 0.40 0.10 0.016 0.004 1.27 0.050 0.05 0.002MIN 1.20 0.047MAX 0.10 MAX 0.004 MAX -8- Rev 2.0 February 1998 |
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